@brouhaha@mastodon.social
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brouhaha

@brouhaha@mastodon.social

#microcontroller #firmware #FPGA #SDR (SW Defined Radio)
#retrocomputing
#nonpareil HP calculator simulation at microcode level
Maker (with John Doran) of Nixie tube RPN calculators
CHM PDP-1 Restoration Team
Damned dirty ape
Call sign N2ES
he/him
cis male
Not a tame programmer
in #Colorado, not far from #Denver

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dangillmor, to random
@dangillmor@mastodon.social avatar

Democrats ask America's most corrupt Supreme Court justice, Clarence Thomas, if he would be kind enough, pretty please, to explain more about his corruption...

He is, of course, not explaining anything -- and daring anyone to do something about it.

https://newrepublic.com/article/181627/clarence-thomas-rv-loan-democrats-letter

brouhaha,
@brouhaha@mastodon.social avatar

@dangillmor
I was once at a restaurant when a firefighter came in with a to-go order for his whole crew. I tried to pay for it, and was politely told that while he appreciated the offer, they weren't able to accept gifts.

It's a sad state of affairs when Supreme Court justices don't have as much ethical integrity as local firefighters.

brouhaha, to kicad
@brouhaha@mastodon.social avatar

Anyone have an open-source #KiCad PCB design that 3D renders with components and looks at least moderately interesting? Doesn't need to be anything specific. I just need a 3D model of a PCB for a demo of a simple program.
I've tried using some projects linked from the KiCad web site, but even for the ones where a rendering is shown on the web site, the only renderings I can get have no components, just the bare PCB. I must not have the necessary libraries.
Thanks!!!

brouhaha,
@brouhaha@mastodon.social avatar

@gsuberland I specifically cloned that repository a few hours ago, opened the board .pro file in KiCad, asked for a 3D render, and didn't get any components other than the reset button and sync header.

brouhaha,
@brouhaha@mastodon.social avatar

@gsuberland I'm using KiCad 8.0.2 on Fedora x86_64.

brouhaha,
@brouhaha@mastodon.social avatar

@gsuberland
Under path substitutions, I see ${KIPPJMOD} as /home/eric/src/glasgow/hardware/boards/glasgow which is the path to the project. Should there be someting more specific?

brouhaha, to random
@brouhaha@mastodon.social avatar

Techbros won't admit that what they're foisting off on us isn't Artificial Intelligence, but rather, Artificial Stupidity. As if we didn't already have more than enough of the natural kind.

brouhaha, to random
@brouhaha@mastodon.social avatar

The real monsters were the people we were along the way.

atomicpoet, to random
@atomicpoet@atomicpoet.org avatar

This is the best way to play VR.

In fact, if I had the space in my house, I’d totally set something like this up.

brouhaha,
@brouhaha@mastodon.social avatar

@atomicpoet Discs of Tron vibe

atomicpoet, to random
@atomicpoet@atomicpoet.org avatar

Social media moderation only works insofar as the one doing the moderating acts in a moderate manner.

brouhaha,
@brouhaha@mastodon.social avatar

@atomicpoet Take nothing to excess, especially moderation!

gsuberland, (edited ) to random
@gsuberland@chaos.social avatar

[serious, no joke replies or guesses / autotranslation please]

do I know anyone native or otherwise very fluent in Chinese who can tell me the correct term for a plated edge connector, like you might find on a PCIe card? specifically the "gold fingers" style connector feature you would find on the PCB side, not the plastic connector it slots into.

I've had an absolute nightmare trying to communicate this feature to a Shenzhen-based PCB vendor and I would like it to be easier in future.

brouhaha,
@brouhaha@mastodon.social avatar

@gsuberland "hard gold edge fingers", which is gold over a layer of nickel, required to prevent the gold aroms from dispersing through the copper.

If you just say "gold edge fingers", you'll get "gold flash", an ultra-thin layer of gold without nickel, which will wear off after only a few mating cycles. Due to the previously mentioned dispersal, it can still look gold after that, while not actually providing the corrosion resistance of hard gold.
1/

brouhaha,
@brouhaha@mastodon.social avatar

@gsuberland PCIe spec says 0.7um (micron) gold over 1.2um nickel. This is IIRC enough to last for 50 mating cycles.

Be very careful about units, as PCB plating used to be commonly specified in uin (microinches), and sometimes still is. 1 microinch is only about 0.03 microns, so if you and the PCB company aren't using the same units, you can get screwed.
If you have to use microinches, the equivalent to the PCIe spec is (obviously) approximately 25 microinches gold over 40 microinches nickel.
2/

brouhaha,
@brouhaha@mastodon.social avatar

@gsuberland Even when they do know, you have to emphasize "hard gold" and plating thickness, or you'll get crap.
I've not personally encountered a Chinese PCB fab that didn't know what gold edge fingers were, but I've mostly used fabs that routinely deal with western customers.
Did you try sending them your photo?

brouhaha,
@brouhaha@mastodon.social avatar

@gsuberland Since you finally got them to understand, can you ask them how to specify it in the future?

RL_Dane, (edited ) to amiga
@RL_Dane@fosstodon.org avatar

Hey folks,

In my little exploration, I'm re-creating the A500 I would've gotten in Christmas 1989 rather than the Macintosh SE I actually got.

My understanding is that the original A500 is capable of displaying 640x400 (NTSC -- I'm in the US) with 4 bitplanes...

So why does workbench display 640x200? (At least, that's what it looks like to me based on the non-square pixels I'm seeing in font rendering)

Update: to avoid interlacing. I forgot abt that 😅
Many thanks for the explanations!

brouhaha,
@brouhaha@mastodon.social avatar

@RL_Dane So that you don't get flicker from interlace.

brouhaha,
@brouhaha@mastodon.social avatar

@RL_Dane Interlace is just as problematic for 625 line 50 Hz, though it can provide 288 lines non-interlaced, vs 240 lines non-interlaced in 525/60.

brouhaha, to random
@brouhaha@mastodon.social avatar

Introducing a revolutionary new software development methodology: WORN

Write Once Run Nowhere

Benefits:

  • Simple to learn
  • Compatible with either Waterfall or Agile development models
  • Ultra-fast compilation
  • No debugging necessary (or possible)
  • Low cost
  • Training courses available
whitequark, to random
@whitequark@mastodon.social avatar

please tell me the most obscure joke you know

(feel free to explain or not explain it, depending on what you find more amusing to think of me reading it)

brouhaha,
@brouhaha@mastodon.social avatar

@whitequark
Q: What's purple and commutes?
A: an Abelian grape

jbqueru, to random
@jbqueru@fosstodon.org avatar

Hmmm. Write Z80 first, then port to 6502? Write 6502 first, then port to Z80? Write 68000 first, then port to both Z80 and 6502? Write a bytecode interpreter on both 6502 and Z80 and then code to that bytecode?

I guess I'm looking for an excuse to think about writing code instead of, you know, actually writing code.

brouhaha,
@brouhaha@mastodon.social avatar

@jbqueru

  1. Define bytecode
  2. Write Turing machine that interprets bytecode
  3. Write Turing machine interpreters for 6502, Z80, etc.
    4.???
  4. PROFIT!
brouhaha,
@brouhaha@mastodon.social avatar

@jbqueru It's not what you expect given those names, though. The 68000 fundamentally has one level of interpretation. The nanocode is partially decoded ROM the provides part of the microinstruction but the same nanocode row is used in multiple microcode rows. There's only one microinstruction sequencer that addresses both ROMs. It's really just a form of ROM compression.

brouhaha,
@brouhaha@mastodon.social avatar

@jbqueru Yes. It's common sequences like controlling a memory write cycle, or setting the condition codes. But it's not really subroutines. They are inline, and act simultaneously with microcode. The "microcode ROM" supplies part of the micro instruction, and the "nanocode ROM" (actually a PLA) supplies a different part, so every microinstruction is made up of both.

brouhaha,
@brouhaha@mastodon.social avatar

@jbqueru It's quite entertaining to me to not-quite-randomly encounter someone else interested in some of the same computer microarchitecture minutiae as I am.
:-)

brouhaha,
@brouhaha@mastodon.social avatar

@pulkomandy @jbqueru The only Surplus/Generalplus chips I've poked at were the 6502 derivatives.
I thought it hilarious that their cheapest ones were a 6502 subset, as if shaving a few transistors off the CPU core was going to materially reduce the chip cost. Clearly it was just product differentiation. Some manage must have said, "Let's drop one of the index registers", so engineers did. But it's even more hilarious that the one they dropped was Y, generally the more useful of the two.

tubetime, to random
@tubetime@mastodon.social avatar

here's a neat and rare bit of hardware: the Comspec SA-1000 SCSI sidecar for the Amiga 1000!

brouhaha,
@brouhaha@mastodon.social avatar

@tubetime I've used a resistor voltage divisor to bias the pin to 1.4V (haflway between TTL receiver thresholds), and two comparators at the thresholds.

brouhaha, to random
@brouhaha@mastodon.social avatar

My HP 16702A logic analyzer has developed bad sectors on the disk, which today prevented me from accomplishing anything while trying to help John with his Z80 system issues.
(Current issue: peripheral card works when directly plugged directly into test CPU board, but not when plugged into test CPU board via an extender board, or into the "real" system with or without the extender.)
The 16702A has an internal SCSI drive. If I had money to spend, I'd get a SCSI2SD to replace that.

eniko, (edited ) to random
@eniko@peoplemaking.games avatar

"The market will efficiently allocate resources where they're most needed!"

Meanwhile, the market: we're putting this "AI" thing that doesn't seem to work and everyone hates into everything you use including your mouse. We're sure this will make us rich somehow. Do you like this? [Yes / Ask me again later]

brouhaha,
@brouhaha@mastodon.social avatar

@justafrog @eniko It doesn't seem like you understand the meaning of "efficient allocation" as used in the market. It means that the largest share is allocated to the person with the most money, and the smallest share (none!). is allocated to the person with the least money. See, it's extremely efficient! Free markets solve everything, including the concern of rich people that poor people might get something they don't deserve, as clearly demonstrated by their lack of money.

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