1/ #TinyTapeout 7 just closed and these two tiles host my design! If it works, it will generate explorable terrain 'voxels' similar to the VoxelSpace Comanche 1992 game engine.
2/ The design is written in #Silice and exported to Verilog, and then synthesized to #ASIC through the amazing #TinyTapeout framework.
The terrain renderer fits on only two tiles, using some tricks 😎. Write-up pending.
UniSuper member Dr Christopher Standen has, through the Environmental Defenders Office (EDO), lodged a complaint with the Australian Securities and Investments Commission (ASIC).
Two of the funds that UniSuper markets as “sustainable” have significant investments in the Transurban Group, one of the world’s largest toll road operators.
“Transurban Group’s business model relies on increasing road traffic, which increases climate and other pollution,” Dr Standen said.
I was wondering what it would cost to have a custom RISC-V based design printed..
...but damb you really do need some really big volume or your own printer if you want to not pay upwards of 1 million for a single CPU-sized die at 16nm, and that's excluding wiring and baking it into a package of any kind
Assuming TSMC's university prototyping pricing, it's about 15k per square millimeter, and for comparison, JUST the non-IO die in a ryzen 5600 is 74mm^2 💸
Moving up in the crypto world ... from gpu miner only I have joined big boys today and bought my first Bitcoin ASIC - Bitmain Antmniner S19K Pro - 120 TH ... I still believe in GPU mining in the next bullrun, so I will continue doing so ... I feel good today ... 😎 😀
Yesterday we released the first numbered version of Surfer, an extensible waveform viewer that runs everywhere 🎉
The big new thing for 0.1.0 is a brand new waveform library written by @ekiwi which supports FSTs, and is much more efficient at handling VCDs than the previous lib. Startup time on a 7GB vcd went from 2 minutes to 6 seconds on my machine 🔥
Ok, Google couldn't help, so suggestions solicitated!
I use both Icarus Verilog and Verilator for simulation and initialize my rams with
$readmemh(`INIT_MEM, code);
The drawback of this is that the produced simulation binary is tied to the
-DINIT_MEM=prog.hex
value used at compilation time. I would like to reuse the simulation binary on multiple workloads. Is there a way that works for both Icarus and Verilator?
As promised, here is part two of my series about the ICPS PDK 🥳️
In this blog post you are going to learn how to design a NAND gate - from schematic to layout.
If there are any issues following the tutorial, please let me know. But most importantly: Have fun!
I've been working on a step-by-step tutorial on how to design a NAND gate using the open source ICPS PDK. It didn't take me long to realize that I'd better explain some of the concepts in a separate blog post, otherwise the tutorial will become too long.
Time for my #introduction to the Fediverse! :masto_love:
Clash is an open source functional hardware description language built on #Haskell.
The Clash compiler allows you to use Haskell features like its strong and powerful typesystem as well as use existing Haskell code and libraries in your #FPGA and #ASIC designs! You can test your designs right inside the REPL, simulate it alongside other Haskell code or output #VHDL / #Verilog / #SystemVerilog code for synthesis.
long-term #conartist extraordinaire, living in #Bali due to #ASIC problems we believe.
He's been ripping off the #vulnerable for years. Prior to that, #anyone who would listen to him.
After a long wait I have in my hands a chip that includes a design I made!
Inside that 3.6x5.2mm piece of glass there is a 0.3x0.3mm portion that includes my project: an adaptation of the HACK cpu from the Nand to Tetris course.
Write tests using Verilator enabling much faster and longer simulations
Install synthesis, place and route tools and simulators in just 1 command via https://github.com/YosysHQ/oss-cad-suite-build. Now you can go from fresh Linux install to a blinky on an FPGA in just a few fully automated commands.
Some context: Spade is my HDL where I try to make it easier and and more fun to program #fpga and #asic by borrowing concepts and philosophies from modern software languages.
“The worldwide BTC mining network consumed 173.42 TWh of electricity during the 2020–2021 period, bigger than the electricity consumption of most nations. The mining process emitted over 85.89 Mt of CO2eq in the same timeframe, equivalent to the emission caused by burning [42 million tons] of coal or running 190 natural gas‐fired power plants.”
@ScottAkenhead And let's not get over the #energy wasted to build #Bitcoin :bitcoin: #ASIC|s, because fabricating custom #silicon that cannot be repurposed for anything at all alongside the #PCBs and auxiliary components takes a shitload of expensive and not envoirementally-friendly materials and an absurd amount of energy.
Compared to i.e. #Monero :monero: where COTS hardware is used that can be used for computing and not end up as #eWaste once it's unprofitable to #mine with...
@greyarea@silverpill TBH, I wish all the #Shitcoins (espechally #Bitcoin :bitcoin: and other #ASIC-mined shit) will die a slow and painful death and that those that have billions sunk into it like #AndreesenHorrowitz will loose everything and have to file for bankrupcy.
Longterm I hope #Monero :monero: will become the new #PayPal :paypal: but in a good way:
As a convenient and fast payment system.
If you are the tiniest bit cryptocurrency-curious, you need to read Zeke Faux's book Number Go Up. Finished it on Sunday. Super-fast read. Totally bonkers stories throughout. The chapter on pig butchering was new to me and yet another damning indictment of the state of the griftswamp.
Emissions from computing are apparently higher than for air travel, and that’ll only go up in the coming decades.
“As a society we need to start treating computational resources as finite and precious, to be utilised only when necessary, and as effectively as possible. We need frugal computing: achieving our aims with less energy and material.”