@azonenberg@ioc.exchange
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azonenberg

@azonenberg@ioc.exchange

Security and open source at the hardware/software interface. Embedded sec @ IOActive. Lead dev of ngscopeclient/libscopehal. GHz probe designer. Open source networking hardware. "So others may live"

Toots searchable on tootfinder.

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azonenberg, to random
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TIL about AMBA CHI (ARM IHI 0050) and CHI C2C (ARM IHI0098).

Is anyone aware of any devices implementing these that are shipping yet?

In particular, I would really like to see a microcontroller-class device with CHI C2C on it.

STM32x7 with C2C anyone? plz?

whitequark, to random
@whitequark@mastodon.social avatar

today's helldivers 2 discovery: it has an unlockable revolver. makes sense, right? lots of games do.

you fire six out of six shots and reload. your character uses a speedloader. makes sense!

you fire two shots and reload.

  • if you're in a fight, your character uses a speedloader, and you lose four
  • if you're not, they reload it round by round, and you lose none

this is an incredible level of attention to detail holy shit. nobody does this!!

azonenberg,
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@whitequark Closest I've seen to that so far is america's army 2.x (never played the newer versions much/at all so can't comment):

  • When reloading a magazine-fed weapon with one in the chamber, you get an extra round (e.g. 30+1 for an M16)

  • The bolt-action M24 sniper rifle models individual-round reloading correctly

  • Removed mags are kept and counted, so you might reload after an intense firefight and have only a bunch of half-full mags

  • Grenades from the M203 have a short range safety and won't go off if they hit something too close

  • The RPG-7 and AT-4 correctly model projectile self-destruct, if you fire off into open space far enough away the round blows up mid flight at some set distance. They also model drop and have adjustable-range sights, as does IIRC the M320 in AA3 (but not the M203 in AA2).

  • The M9 pistol slide locks back on an empty mag and your character does a "slingshot" slide release. Can't remember if they modeled this for the M4/16 or not.

  • Breathing is modeled reasonably well.

But there's some bugs too: IIRC if the pistol jams on the last round in the mag, the slide will drop rather than locking back after you eject the dud cartridge. And I think the reload animation for the (belt fed) M249 doesn't show a partial-length belt if you have only a handful of rounds left, although I think they do have two animations for reloading from "mostly full" and "empty".

And all of the small arms are hitscan.

azonenberg,
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@whitequark They also model three stances (standing/crouching/prone) plus movement with accuracy affected by each, as well as a bipod you can deploy when prone to get maximum accuracy.

Accuracy is also impacted by health status and heart rate, so for example if you sprint somewhere then dive into prone, or have a whole bunch of enemy fire narrowly miss you, your accuracy will be garbage for a bit.

azonenberg,
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@whitequark The damage model for all of the AA games was pretty good as well, you'd take some initial damage on a hit then a lot more over time from bleeding (the percentage of each would depend on the type of injury and where you got hit).

You have a field dressing you can apply to slow (but not completely stop) bleeding but a medic-trained teammate has to treat you to fully stop it.

Rounds will go through players or many objects in the game world although they lose energy and IIRC might deflect slightly.

azonenberg,
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@whitequark IIRC AA3 also improved the damage model to account for limb vs torso hits having different effects on your performance (e.g. a leg injury, even if treated, reduces your movement speed while an arm injury impacts your accuracy more). But I could be wrong, I never played 3 much.

2.x had a single global HP value, the only time the damage model accounted for location was when calculating damage caused by a hit.

Oh, and grenades actually did (range limited) hitscan modeling for individual fragments to calculate damage, including reduction of damage by cover slowing down/blocking them.

azonenberg,
@azonenberg@ioc.exchange avatar

@whitequark The Long Dark has a well modeled rifle in this regard. It's an old Lee-Enfield that takes two five-round stripper clips in a ten round mag.

On the rare occasions you find enough ammo to reload five or ten rounds at a time you'll use 1-2 clips. For anything else, you're pushing in single rounds one at a time.

But we're talking post-apocalyptic survival here, not FPS, so ammo is scarce and combat is best avoided. The bow and arrow is much more renewable (not infinitely as maple saplings for the bow and birch for the arrow shafts spawn in finite quantity in the game world, but they're far less scarce than ammo and materials for crafting more).

azonenberg,
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@whitequark (TLD seems like your kind of game... In survival mode everything is trying to kill you, including the weather. Except some of the animals you can eat)

azonenberg,
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@whitequark Speaking of weather it's quite realistically modeled since it's one of your main threats (hypothermia will kill you faster than pretty much anything but a bear or wolf attack).

There's an ambient temperature plus wind chill and precipitation. Every piece of clothing has a certain level of insulation and windproofness, as well as waterproofness. Wet clothing is far less warm and also can soak through to layers underneath.

Skin left exposed to freezing weather, or touching wet clothing that's left outside long enough to freeze, can develop frostbite which gives you a permanent health reduction.

Carrying a heat source warms you slightly, but road flares are non renewable and extremely scarce, oil for your lamp has to be looted or rendered from cooked fish, and torches can be blown out by the wind.

Oh, and clothing wears over time and can be damaged by animal attacks, snagging on things during a fall, etc. And can be repaired with a sewing kit or (more slowly) with crafted materials. And worn clothing has less insulation etc.

azonenberg,
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@alloydflanagan I have close to 1K hours and recently completed the last achievement (survive 500 in-game days).

It's my main game these days. definitely recommended.

azonenberg, to random
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Well that was fun. Spent probably 45 minutes troubleshooting my RTL before looking at the post-synthesis netlist in Vivado and discovering that somehow incremental synthesis had got stuck on a stale version of the netlist, based on an old version of my RTL.

I was changing the source code and seeing the netlist completely unmodified. I tried being increasingly aggressive, to the point of deleting the entire .cache directory under the project, before finally finding the setting to completely disable incremental synthesis which seems to have solved the issue.

azonenberg,
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@bl0x I didn't even know it was on by default.

azonenberg, to random
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New conspiracy theory: LLMs were invented as a secret project by a global cabal of compliance and IP attorneys seeking to ensure their continued employment prospects.

tef, to random
@tef@mastodon.social avatar

not to call ai a big woop of nothing but slack absolutely slaughtering any remaining trust they have in order to provide "emoji suggestions" is incredible

azonenberg,
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@tef I felt a great disturbance in the Force, as if millions of ITAR/export compliance lawyers cried out in terror and were suddenly silenced.

azonenberg, to random
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Soooo I think I may have finally put a bookend on my UPS saga.

Background: during the power outages a few weeks ago, I had the UPS shut down twice (once during the initial outage, second during generator fuel tank refill) when the battery gauge suggested i should have had plenty of juice left.

The first Eaton support guy I talked to said the unit was defective and I had to scrap it and shell out >$4K for a new UPS. Obviously I decided to do a bit more digging before taking that step.

Well, turns out after talking to another support rep that I've been hit by a 9PX series firmware bug he's seen once in his career. Conditions which are not fully understood (but are possibly related to swapping the network management card) result in the "low battery warning" threshold being set to 90% instead of the default 20%. This setting is apparently confusingly named and is actually the low battery shutdown threshold.

So it was draining 10% of the UPS capacity then shutting down thinking the battery was empty.

azonenberg, to random
@azonenberg@ioc.exchange avatar

Some insights from my last poll (apparently it's not possible to make a "anyone can see, only followers can vote" poll so it's followers-only)...

Roughly 1 in 6.5 of my followers are trans (about three times the 5% rate reported in a Pew Research survey from 2022). Of the trans folks, about a third are also furries.

I figured there would be a lot of each, but the amount of overlap (especially the lack of cis furries) surprised me: if you're furry and follow me, there's a 71% chance you're trans.

Stormgren, to random
@Stormgren@obsidianmoon.com avatar

The fact that there are QSFP and OSFP pluggable EDFAs somehow feels sorta wrong. I really don't want to know how noisy those things are, and yet, I can see how useful they might be for datacenter interconnect types. I hate to lose switchports to something better handled by a 1U combiner/amplifier shelf in that application.

Though the fact that this means that the CS connector has gained traction as a result is also not making me happy, because what we needed was something even SMALLER than LC, said no one ever. Like, seriously? At least it's push-pull instead of locking tab.

azonenberg,
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@Stormgren My azonenberg/latentpacket repo has all of the networking stuff but yeah I probably need to update the high level project docs.

The high level goal is a layer 2 (to start), possibly with some layer 3 functionality in the future, switch that's simple, no frills, and fast.

I don't need support for 30 different kinds of multicast routing and DECnet and AX.25 and IPoAC.

Just give me a basic, 1990s style fixed function CAM ASIC style, switch with as few features and as little attack surface as possible, but also modern 10/25G interface support and good power efficiency.

So the vision is a switch with a dedicated 1000baseT SSH management interface and RS232 console port connected to the management CPU, while all switch fabric ports are completely independent of management and cannot talk to the management engine (there will be no "slow path", the CPU cannot see traffic going to/from switch ports).

I don't need a lot of bells and whistles. Just port based VLANs, 802.1q, ability to force ports to specific speed and maybe duplex states, access to diagnostics like performance counters and error rates, and probably eventually some kind of port mirror/capture capability.

azonenberg,
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@Stormgren LATENTPINK was the scaled down R&D testbed (which is switching packets now including port VLANs and inbound 802.1q, but has incomplete support for outbound 802.1q tag insertion) with only 12 ports and a single SFP+ uplink.

This used a Kintex-7 FPGA (XC7K160T) but it filled up fast enough that I didn't think I would be able to fit my initial 24 port goal into the same space.

The new concept for LATENTRED scales up to an UltraScale+ FPGA and 36-48 ports (dependent on which FPGA I go with, as well as exact details of things like front panel layout).

azonenberg,
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@Stormgren Yeah I have plans for higher end hardware with at least 100G on it, but that's going to be the successor (LATENTORANGE). Mix and speed of ports is TBD.

I plan to build two LATENTRED systems to replace my four aging Catalyst 2970G's, then at some point in the indefinite future after that, replace my Nexus 3064X with a LATENTORANGE.

azonenberg, to random
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New thread on my big ongoing embedded project since the other one was getting too big.

To recap, this is a pilot project for a bunch of my future open hardware T&M and networking projects, validating a common platform that a lot of the future stuff is going to run on.

The primary problem it's trying to address is that I have a lot of instrumentation with trigger in/out ports, sometimes at different voltage levels, and I don't always have the same instrument sourcing the trigger every time.

So rather than moving around cables all the time and adding splitters, attenuators, amplifiers, etc. to the trigger signals I decided to make a dedicated device using an old XC7K70T-2FBG484 I had lying around.

Of course, as with any project, there was feature creep.

I'm standardizing on +48V DC for powering all of my future projects as it's high enough to move a lot of power but low enough to be mostly safe to work around live. So I needed to design and validate an intermediate bus converter to bring the 48 down to something like 12 for the rest of the system to use.

The FPGA has four 10G transceiver pairs on it. I used one for 10GbE (not that I need the bandwidth, but I was low on RJ45 ports on this bench and had some free SFP drops) and the rest are hooked up to front panel SMA ports (awaiting cables to go from PCB to panel) to generate PRBSes for instrument deskew.

Since I'm pinning out the transceivers and am planning to build a BERT eventually, I added BERT functionality to the firmware as well (still need to finish a few things but it's mostly usable now).

And since I have transceivers and access to all of the scope triggers, it would be dumb not to build a CDR trigger mode as well. That's in progress.

azonenberg,
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Almost done with the APB refactoring despite lots of other things going on keeping me from spending a lot of time on it.

Now at 40% LUT load so plenty of room to expand for new features (in particular, CDR triggering) in the future.

Purple on south edge = Curve25519 accelerator

Pink at north area: debug ILA, currently looking at CDR trigger signals in anticipation of me actually implementing CDR trigger functionality at some point

Dark blue mostly in northeast: BERT / CDR trigger subsystem

Light blue: Ethernet MAC/PCS logic

Green: actual trigger crossbar muxing (tiny portion of overall logic, lol)

Red = management logic (QSPI bridge, legacy bus logic, FIFOs for MCU Ethernet TX/RX)

Brown = low speed APB peripherals (tachometers for fans, front panel SPI bus interface, etc)

Still some additional refactoring and code cleanup pending, plus converting the 1000baseT TX FIFO, the shared Ethernet RX FIFO, and the interrupt status register to APB. Hoping to get that done in the next couple days.

azonenberg,
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@FenTiger In my case, the accelerator block is mostly there because I was tired of waiting for the STM32 to initialize a SSH session doing software crypto.

Overkill? Probably. But I had the free FPGA space, so why not?

azonenberg,
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More progress: TX FIFO and status register are now on APB, leaving the Ethernet RX FIFO as the last remaining block on the legacy bus.

Very close to being ready to nuke it entirely, at which point I can start working on the memory mapping - the ultimate goal of this refactoring.

azonenberg,
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RX FIFO is now converted to APB, and I found and removed one of two unnecessary CDCs in the process (the other will be more work and I'll keep for a while).

Now chasing an apparently-harmless bug in which I get a zero-byte packet (start/commit pair with no data) before an actual frame. But I don't like it and want it fixed.

azonenberg,
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And fixed it, bad handling of inter-frame gaps.

So, here we are like a week later and I think I've shaved every last yak between me and memory mapping the FPGA over QSPI!

Here goes nothing.

azonenberg, (edited )
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Well, this was an adventure but I have the first couple of peripherals working in memory mapped mode!

Got bit by yet another STM32H7 silicon bug, it took me a whole 20-30 minutes of staring at my code (and fixing unrelated bugs) before I opened up the errata sheet and found the problem: memory mapped writes will return a bus fault unless DQS is enabled.

The workaround is simple: set the "use DQS" bit in the write configuration register, then if you're using a bus that doesn't actually need DQS (like I am), just don't set the alt mode on DQS to connect to the peripheral.

This works great... as long as you don't accidentally enable DQS on reads as well.

If you do that, you'll deadlock the AHB bus on the STM32. Which will completely freeze the processor (to the point that it's unresponsive over JTAG, since CoreSight uses the same AMBA fabric rather than a dedicated APB bus as is the case with a lot of higher end SoCs).

Now your micro is soft-bricked and the only way to recover it is to spam resets and JTAG halt requests at it, and hope to win the race by freezing the CPU before it gets to the first memory mapped read.

azonenberg,
@azonenberg@ioc.exchange avatar

Anyway, more code refactoring needed to use memory mapped IO for more peripherals, plus I need to investigate why memory mapped writes to the Ethernet transmit buffer aren't working (should be an easy fix, i already suspect i know what's going on).

But the bus bridging is actually working! Cortex-M7 AXI -> STM32 internal AHB -> OCTOSPI peripheral -> LVCMOS33 quad SPI -> FPGA internal APB -> on-FPGA peripherals. Memory mapped end to end.

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