The fact that there are QSFP and OSFP pluggable EDFAs somehow feels sorta wrong. I really don't want to know how noisy those things are, and yet, I can see how useful they might be for datacenter interconnect types. I hate to lose switchports to something better handled by a 1U combiner/amplifier shelf in that application.
Though the fact that this means that the CS connector has gained traction as a result is also not making me happy, because what we needed was something even SMALLER than LC, said no one ever. Like, seriously? At least it's push-pull instead of locking tab.
@Stormgren Wait, so it ignores the host facing serdes lines and just uses it for power? Optical in, optical out, using the sfp form factor because of convenience??
I am waiting on my arista account to be activated again and permissions granted, to confirm,but it also looks like there's likely I2C/CMIS access to adjust amp gain and read optical parameters off the module as well.
The SERDES aren't specifically needed because no data is going through them at all.
I've been looking into 400G ZR+ "bright" (read up to 1dB launch power) optics, and fell down an Arista datasheet hole. :P
@Stormgren Yeah I figured there were diagnostics on the I2C.
But as an FPGA guy who is used to scrimping and saving to put every last transceiver lane to good use, the idea of a QSFP that just ignores them rubs me the wrong way :)
@azonenberg As someone who has done a lot of switch deployment engineering and does optical transport mostly these days, they're offensive on so many levels, and there's a bunch of companies doing this sort of thing,
Solid Optics has a QSFP-DD EFDA pluggable, for example. There is also so many colorless splitter/combiners that are just fanout cables. It's like they're doing everything to make a spaghetti mess of fiber cables just to avoid doing stuff in an additional 1-2RU.
@Stormgren You want something really insane / offensive, try my dream (which I never had time to implement) of shoving an ESP32 or similar into a SFP+ form factor with a single SMA connector on the front.
Slap it in a switch port and turn it into a single antenna (non MIMO) wifi AP.
@Stormgren But that was mostly a "for the lulz" concept not something I seriously planned to deploy anywhere.
My own switch designs are going to be far more sane, for LATENTRED I'm now looking at 2x SFP28 uplink + 48x 10/100/1000baseT RJ45 ports (4x VSC8512 12-port QSGMII PHY line card)
@azonenberg The power limits might get ya first, but then again, there's all those wacky linux plugs and self-contained PON OLT pluggables out there that show otherwise. :)
Do you have a link to summarize what LATENTRED is supposed to end up doing in the end? I've been following your design work with great interest, but have missed what the goal is supposed to be. :)
@Stormgren My azonenberg/latentpacket repo has all of the networking stuff but yeah I probably need to update the high level project docs.
The high level goal is a layer 2 (to start), possibly with some layer 3 functionality in the future, switch that's simple, no frills, and fast.
I don't need support for 30 different kinds of multicast routing and DECnet and AX.25 and IPoAC.
Just give me a basic, 1990s style fixed function CAM ASIC style, switch with as few features and as little attack surface as possible, but also modern 10/25G interface support and good power efficiency.
So the vision is a switch with a dedicated 1000baseT SSH management interface and RS232 console port connected to the management CPU, while all switch fabric ports are completely independent of management and cannot talk to the management engine (there will be no "slow path", the CPU cannot see traffic going to/from switch ports).
I don't need a lot of bells and whistles. Just port based VLANs, 802.1q, ability to force ports to specific speed and maybe duplex states, access to diagnostics like performance counters and error rates, and probably eventually some kind of port mirror/capture capability.
@Stormgren LATENTPINK was the scaled down R&D testbed (which is switching packets now including port VLANs and inbound 802.1q, but has incomplete support for outbound 802.1q tag insertion) with only 12 ports and a single SFP+ uplink.
This used a Kintex-7 FPGA (XC7K160T) but it filled up fast enough that I didn't think I would be able to fit my initial 24 port goal into the same space.
The new concept for LATENTRED scales up to an UltraScale+ FPGA and 36-48 ports (dependent on which FPGA I go with, as well as exact details of things like front panel layout).
@Stormgren Yeah I have plans for higher end hardware with at least 100G on it, but that's going to be the successor (LATENTORANGE). Mix and speed of ports is TBD.
I plan to build two LATENTRED systems to replace my four aging Catalyst 2970G's, then at some point in the indefinite future after that, replace my Nexus 3064X with a LATENTORANGE.
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