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mattpd

@mattpd@mastodon.social

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mattpd, to random
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mattpd, to random
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A Simple showcase for the Sea-of-Nodes compiler IR
https://github.com/SeaOfNodes/Simple
Chapter 9: Global Value Numbering. Iterative peepholes to fixpoint. Worklists.

mattpd, to random
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How Badly Do We Want Correct Compilers?
https://www.youtube.com/watch?v=tMYYrR-hazI
John Regehr (@regehr) - NDC TechTown 2023

mattpd, to llvm
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How single-iteration InstCombine improves LLVM compile time
https://developers.redhat.com/articles/2023/12/07/how-single-iteration-instcombine-improves-llvm-compile-time
by Nikita Popov

Migueldeicaza, to random
@Migueldeicaza@mastodon.social avatar

Microsoft’s Maia chip for hardware acceleration uses a new set of numeric data types to speed up computation. It used to be called internally msfloat, but is now becoming an open standard with a consortium of companies behind it.

This format requires that the data use the same exponent, and only differ in the sign/mantissa. So you can move a lot more of these numbers in one go:

https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf

mattpd,
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@Migueldeicaza @rhempel @jripley BTW, would you happen to know whether the approximation properties of the Dot and DotGeneral MX operations have been standardized? Context: a nice post by @gconstantinides, https://constantinides.net/2023/10/30/industry-coheres-around-mx/ (also pointing out the historical block floating point background).

mattpd, to llvm
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2023 LLVM Developers' Meeting Trip Report by Henrich Lauko
https://xlauko.github.io/2023/11/10/llvm-dev-met.html

chandlerc, to random
@chandlerc@hachyderm.io avatar

FYI & note to future self for easier finding and referencing Arm and Neon intrinsics:

https://arm-software.github.io/acle/main/acle.html
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html

These are much more effective than the ARM developer site -- can just use normal search, and they even include things bizarrely missing on the ARM developer site like vst1_*.

(I've probably been directed at these at least twice before, but maybe by posting this will help me remember the right place to go for the reference...)

mattpd,
@mattpd@mastodon.social avatar

@chandlerc FWIW, if you also need asm instructions, I've found "Arm A64 Instruction Set Architecture" to be pretty navigable:
https://developer.arm.com/downloads/-/exploration-tools

Note: not "View HTML" but "Download XML", a tarball which has a PDF and a directory corresponding to the version (e.g., "ISA_A64_xml_A_profile-2023-09"): unpack that, open "index.html" in your web browser, and you'll get a pretty convenient instructions manual (with top bar allowing to navigate between the BASE, SIMD&FP, and SVE instructions).

mattpd, to random
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Facile: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction
https://arxiv.org/abs/2310.13212
IEEE International Symposium on Workload Characterization (IISWC) 2023
Andreas Abel (https://uops.info/), Shrey Sharma, Jan Reineke

image/jpeg

mikenicolella, to random

Are there some resources out there to learn more about how database storage works? Like, what does the layout of the files on disk look like? What kind of structure is used to store the ‘current’ version of the DB? How do they achieve robust atomic updates? That sort of stuff. Would prefer to just learn about one particular implementation versus the academic theory.

mattpd,
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@mikenicolella CMU DB lectures from https://15445.courses.cs.cmu.edu/fall2023/schedule.html (starting from "Lecture #03: Database Storage I") and https://15721.courses.cs.cmu.edu/spring2023/schedule.html (starting from "#03 — Storage Models & Data Layout") are pretty good, most have multiple examples from/comparing practical DBMS implementations.

pervognsen, to random
@pervognsen@mastodon.social avatar

I'm trying to find posts about this but my Google-Fu is letting me down: does anyone remember something about a microcode bug for one of the Zens where RDTSC had drastically reduced granularity?

mattpd,
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@pervognsen Take A Way: Exploring the Security Implications of AMD’s Cache Way Predictors
https://mlq.me/download/takeaway.pdf
Section 2.3, 2.3 High-resolution Timing & Appendix A, RDTSC Resolution

AMD Prefetch Attacks through Power and Time
https://mlq.me/download/amdprefetch.pdf
Section 3.1, Leakage Analysis Primitives

(AMD Zen 2 or newer: 36 cycle update interval using rdtsc/rdtscp/MPERF; however, still 1 cycle update interval reading APERF using rdpru).

neilhenning, to random
@neilhenning@mastodon.gamedev.place avatar

Anyone know if there are any rough stats for the % of functions that are hot / medium / cold in most codebases?

I know that this is gonna be super application dependent - but I'm curious what the rough shape of these numbers would be for your average blob of code.

Hot being hit all the time, cold being hit never or almost never, medium being the rest.

mattpd,
@mattpd@mastodon.social avatar

@neilhenning "even among the hottest and most well-optimized functions in our server fleet, more than 50% of code is completely cold."
"Not only is more than 50% of code cold, but it is also interspersed between the relatively hot regions, and likely unnecessarily brought in by prefetchers." - from "AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers", https://research.google/pubs/pub48320/

regehr, to random
@regehr@mastodon.social avatar

I found the guy! someone hire him quick!!!

mattpd,
@mattpd@mastodon.social avatar

@zwarich @regehr I'd go with pointer provenance, there's a brief DR, https://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_260.htm, should be an easy freebie!

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