@Houl The 6502 did not have a reasonably orthogonal instruction set which means it isn't RISC. Some people would add the lack of a flat memory model, but that just makes it a poor C target.
I love the 6502, but I personally wish zero page could be moved around -- something WDC variants call direct page -- and the stack could similarly be relocated. The first change would increase performance a lot and the second would make real multitasking possible.
@ted_dunning@Houl Can you explain what this means? All I know about #SPARC is that #Oracle bought #Sun and lied their asses off about future development of the platform, bailed, and promptly screwed EVERYONE with a stake in the platform. That's it. Oh, and #Gentoo can boot it. But since Gentoo is the #NetBSD of the Linux world so that's not a surprise. "Of course it runs Gentoo!"
Probably the most interesting feature (at the time) for the Sparc architecture was the use of register windows. The basic idea is that the processor has 32 general purpose registers divided between globals, "in", "local" and "out". When you make a call, the processor renames things a bit so that the out registers become the in registers at the next call level.
Register windows are a bit like a (small) page zero because you can get to them with a short address. Being able to efficiently roll to the next window was pretty cool and is like being able to have a new page zero when you call a function.
In fact, however, register windows turned out very bad if you account for context switches because tons of unused registers had to be flushed to the stack.
@ted_dunning@Houl That was exactly the kind of thing I wanted to know. I'm an #assemblylanguage geek. Thanks! I've cough spent more time looking at #motorola#M6809 documents today than I should have. Damned ADHD. :-P
Do you think the arch will live on in some way? Even #Fujitsu bailed on it.
That sort of thing lives longer than anybody can believe, but I really don't see a lot of room. x86, ARM and Risc-V don't leave a lot of oxygen to spare.
Being open source doesn't help with Sparc's fundamental problem with spilling register windows on context switch. Because many of the spilled registers are actually not even used this is very wasteful of memory bandwidth.
Better to do what modern processors do and treat L1 cache as a huge register pool. Small flips can have small cost that way.
The net net is that Sparc won't have a revival no matter what. RiscV fixes the problems and thus wins.
Pretty shure a low power yet #64bit version may have it's merits in #embedded and #automation, espechally if it could be hooked up directly to 5V without need to step-down...
Not shure if it could compete with the @Raspberry_Pi#PiPico (W) unless there's some substantial demand for #DIP40 ir as drop-in #upgrade...
Add comment