@nota it has been implemented in some GDDR stuff but there's literally no reason to use it, it's functionally pointless.
QDR is similarly not very useful. DDR is sensible because if you switch data signals once per clock cycle your clock ends up having twice the Nyquist rate as your data, so by sampling data on each edge you bring the data Nyquist rate up to the clock Nyquist rate and everything has the same design requirements. but with QDR you re-introduce the imbalance, but backwards.
@nota as far as I can tell the reason they put QDR/ODR into some GDDR stuff was related to some specific implementation details around how clocking works in some designs, in relation to power saving modes, but I have never been able to find a concrete explanation.
@gsuberland I'm told QDR does get used a fair bit in networking stuff, with one channel being writes and the other reads. Basically two DDR channels but 90° apart. Since with networking that's usually fairly symmetric and you don't want the latency hit of having to switch between the two or have them contend with each other.
@nota hmm, it seems like interleaving would make more sense though, since that way you avoid needing a clock-doubling PLL to sample the extra phases and you keep everything at the same Nyquist rate. but networking stuff is often weird so maybe there's a good reason to do it that way.
@gsuberland@nota So-called QDR RAM is actually two DDR ports, one for reads and one for writes (in older generations) or two bidirectional (for newer). But normally they're sharing one common clock not 90 deg phased.
@gsuberland@nota Not really. QDR-II+ (only family I have specific experience with) is one parallel command/address bus at single rate, alternating issuing requests to the read and write data buses (BL=4, DDR).
@azonenberg@nota now I'm confused again. when I said "kinda like QSPI" I meant in the sense that they're increasing bus parallelism at the exact same transmission rate instead of sending more data per second down the same number of lines. is that not what they're doing? the "alternating" part isn't clear to me here (I also don't know what BL=4 means)
So at T=0 you send a write enable and write address, then at T=1/1.5/2/2.5 you send write data.
At T=1 you send a read enable and read address, then at T=2/2.5/3/3.5 you get read data (simplifying a bit since there's usually some read latency, but you get the idea).
Then at T=2 you can issue another write, and so on.
There's no hard requirement that you have a strict even/odd alternation of reads and writes, but it makes controller design simple and lets you saturate both data buses so it's the logical way to do it.
@gsuberland@nota It's more like regular SPI than QSPI in that it's full duplex with separate read and write data buses active simultaneously (just that each bus is 18/36 bits wide).
@azonenberg@nota right, so the "QDR" part is that they're giving you separate ports for read/write, effectively making it full duplex (subject to command patterns) instead of half duplex? but the signalling on the lines themselves is still just DDR in terms of being sampled at both edges, right?
@azonenberg@nota so is QDR (the signalling thing, not the multi-port misnomer) actually used for anything? it seems pointless to me but sometimes things surprise me.
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