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resistor

@resistor@mastodon.online

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resistor, to random
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AltiVec+RISC-V: keep the reg+reg addressing modes? Or conform to RISC-V standard practice and do reg+imm?

resistor, to random
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Quick and dirty encoding of Altivec into RISC-V: https://gist.github.com/resistor/bc82bd259b662084a5950ac9b863d8c2

resistor,
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@chandlerc Probably? ARM usually does a good job at encoding things densely.

Part of the thesis here is that AltiVec is more than 20 years old, so there can’t be any patent issues preventing gluing it directly onto RISC-V.

resistor, to random
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searches for RISC-V soft core to experiment with

looks at first result

Of course it’s from @whitequark 🤣

resistor,
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resistor,
@resistor@mastodon.online avatar

@whitequark Ah, I just saw your name on the several most recent commits.

Still, it would have been completely on-brand for you for this to have occurred.

resistor,
@resistor@mastodon.online avatar

@whitequark Should I add Altivec to it? ;-)

resistor, to random
@resistor@mastodon.online avatar

Modern chat systems, whether direct, group, or community, fail to capture the joy of 90s IM systems for me.

The inherently synchronous experience, knowing that the other person was also sitting at their PC on the other end, made it much more like hanging out in person than any modern system.

resistor,
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IRC, though dying, still captures some of that feeling. But I miss sitting down in the evening, seeing which of my friends were also online, and striking up a casual conversation.

resistor,
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@whitequark I spent so many evenings in #llvm 😰

whitequark, to random
@whitequark@mastodon.social avatar

every compiler project expands until it creates its own version of TableGen. after that it is swiftly replaced with something that is "not as difficult to use", and the cycle continues

resistor,
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@whitequark Except for TableGen itself. TableGen is eternal.

pervognsen, to random
@pervognsen@mastodon.social avatar

I've never fully worked out how best to articulate my dissatisfaction with the usual way people talk about pluggable allocators in systems programming. Sure, I'd like to have some standard for fallible, pluggable allocation at the lower level of a language's standard library. But the entire mindset of plugging together allocators and data structures is something I find dubious and at best it feels like a poor compromise.

resistor,
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@pervognsen I think this view doesn't sufficiently consider the fact that requirements change, and that a system may need to have its allocation strategy changed without a complete rearchitecting due to that.

pervognsen, to random
@pervognsen@mastodon.social avatar

The age of bad AI-generated logo art for open source projects is upon us.

resistor,
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@pervognsen A color scheme that borders on chromatic aberration seems to be a common theme in AI-generated logos for some reason.

resistor, to random
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uarch shower thought: Register windows, which have more or less died out, trade area (and specifically on-die storage) for latency (fast subroutine return).

Techniques that trade on-die storage area for bandwidth (vectorization, register renaming, many forms of OOO, SMT, etc) are still going strong, especially if you think of GPUs as big vector SMT machines.

Is it fundamental that area-for-latency is a bad uarch tradeoff in the long run?

resistor,
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@pervognsen That dates back to the late 90s, right?

resistor,
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@pervognsen I only recently learned that the AMD 29K also had register windows (courtesy of miroarch club podcast)

resistor,
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@pervognsen Probably well on its way to being eaten by RISC-V in most places, but I'm sure there's a lot of LEONs in weird places that will keep ticking away for a long time.

resistor, to random
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@whitequark Do you know if anyone has written about best practices for designs in Amaranth (or maybe just HDL in general)? I feel like I'm at a point where I can write HDL that does the job, but rapidly devolves into spaghetti as it gets bigger.

regehr, to random
@regehr@mastodon.social avatar

an LLVM developer and I weren't seeing eye to eye on a miscompilation, and it turns out the AArch64 backend is doing different codegen when invoked via clang vs invoked via llc 🤯

https://github.com/llvm/llvm-project/issues/88950

resistor,
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@whitequark @regehr Target flags implied by target triples is usually what gets me.

resistor,
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@regehr @whitequark The .ll file will contain the target triple, you just need to disable the filtering in godbolt

resistor, to random
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Just got hit in the ear by an enormous flying fish while sitting under the coach roof in the cockpit. Achievement unlocked?

resistor, to random
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After months (years, really) of preparation and build up, we’re pushing off to leave the Americas in our wake tomorrow, bound for the Marquesa Islands in French Polynesia. A solid month at sea, and then a whole new side of the world. Excited and nervous at the same time…

regehr, to random
@regehr@mastodon.social avatar

UW is youdubbing extra hard today

resistor,
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@regehr I loved walking through that area when they were in bloom!

whitequark, to random
@whitequark@mastodon.social avatar

holy shit the english trains are unusable

resistor,
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@whitequark You’re living a real life MTA song: https://www.mit.edu/~jdreed/t/charlie.html

chandlerc, to random
@chandlerc@hachyderm.io avatar

For C++ library folks -- should const on containers propagate to the elements in the container? why? (or why not?)

And if "yes", why should span (or equivalent) not take the same path? Or should it?

(To be clear, I have lots of my own thoughts on all of these questions. I'm not asking because I'm unaware of any possible answers, but to see how others think about them.)

resistor,
@resistor@mastodon.online avatar

@chandlerc I don't follow, can you sketch something out?

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