The elegance of the DG Nova instruction set really becomes apparent when you write emulation code for it. The entire core CPU emulation (no devices) is 250 lines of C, including comments and not even written to be small.
Nova 3 and 4 will probably add another 50-100 lines at most
Now, after reading it, I have one question you might be able to explain.
It says the following:
Hence, location 1 must contain the start address of the interrupt handler. When an interrupt happens, further interrupts are disabled until they are explicitly re-enabled. A return from the interrupt is performed by jumping indirectly through location zero (i.e. JMP @0).
Earlier in the document, it's explained that interrupts are enabled using the INTEN instruction, so if I read the correctly, the end of the interrupt handler should be an INTEN followed by JMP @0.
But what happens if there is another interrupt after enabling it, but before the jump is done?
@loke If you are nesting interrupts you store the contents of 0 somewhere else then either put it back when ready or jump through the saved version.
The other detail is that INTEN takes effect one instruction after not immediately - ie it's the same trick the Z80 later did so you can EI RETI, but in the Nova case you can INTEN JMP @0
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