TSMC’s debacle in the American desert (restofworld.org)
Intel Receives ASML’s First High NA EUV system (www.youtube.com)
Synopsys to acquire graphics software maker Ansys in $35 billion tech deal (www.cnbc.com)
Chip Packaging Trumps EDA: Why Synopsys Is Paying $35 Billion For Ansys (www.nextplatform.com)
Polynomial Formal Verification: Verification-Centric Strategy (agra.informatik.uni-bremen.de)
As formal verification becomes more common in the industry, design complexity continues to be a challenge. Article argues that this is a byproduct of design-centric approach (optimize area, power, speed) without considering verifiability. A verification-centric approach driven by polynomial formal verification analysis can...
5 Steps to Confront the Talent Shortage With IP-Centric Design (www.eetimes.com)
One way to help alleviate the effects of the talent shortage is changing how semiconductors are designed so that organizations can achieve more with their existing workforce. This requires moving away from project-centric design and transitioning to an IP-centric design methodology....
Chip Industry Talent Shortage Drives Academic Partnerships (semiengineering.com)
So how can universities train students for a continuous and rapidly changing technology? This is especially difficult because it involves both software and hardware, and more domain-specific and increasingly heterogeneous architectures. And regardless of whether these devices are tethered to a battery or plugged into a socket,...
Google's Controversial AI Chip Paper Under Scrutiny Again (www.hpcwire.com)
Using LLMs to Facilitate Formal Verification of RTL (arxiv.org)
Engineers in Princeton managed to train GPT4 and extend AutoSVA to generate SVA (systemverilog assertions) from buggy RTL and functionality description. SVA is widely used to verify digital design for ASIC and FPGAs. AutoSVA2, which extends open-source AutoSVA, improves the flow to generate SVA from English description. LLM was...
Growing full wafers of high-performing 2D semiconductor that integrates with state-of-the-art chips (techxplore.com)
One of the biggest shortcomings of silicon is that it can only be made so thin because its material properties are fundamentally limited to three dimensions [3D]. For this reason, two-dimensional [2D] semiconductors—so thin as to have almost no height—have become an object of interest to scientists, engineers and...
Test Strategies In The Era Of Heterogeneous Integration (semiengineering.com)
Compared with traditional monolithic devices, the design and manufacturing process for chiplets is significantly different. The scrap costs associated with manufacturing traditional monolithic semiconductor devices is basically linear, including single chip cost, packaging, and assembly costs....
Use Cases And Value Proposition Of eFPGA (Embedded FPGA) (semiengineering.com)
Many volume applications use FPGA because they need in-field reconfigurability (changing standards, changing algorithms, etc) but they want to improve their system’s competitiveness (power, size, cost). FPGAs are bulky, expensive and power hungry. Integrating eFPGA can greatly improve the economics while maintaining full...
Challenges In Ramping New Manufacturing Processes (www.youtube.com)
semiengineering.com/challenges-in-ramping-new-man…...
Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows (www.cadence.com)
The digital RAKs provide Arm Neoverse V2 designers with several key benefits. For example, the Cadence Cerebrus AI capabilities automate and scale digital chip design, delivering better PPA and improving designer productivity. Cadence iSpatial technology provides an integrated and predictable implementation flow for the faster...
The dream of a chiplet marketplace is still a long way off (www.google.com)
How Dead Is Moore's Law? (Sabine Hossenfelder) (piped.video)
cross-posted from: lemm.ee/post/4443753...
Tensor Processing Units: History and hardware (www.youtube.com)
German investment in open-source chip design (www.elektronikforschung.de)
The German Federal Ministry of Education and Research announces to fund the development of an open-source chip design ecosystem. This includes also design software.
Free Silicon Conference 2023, Paris, July 10-12 (wiki.f-si.org)
Diverse talks about chip design with open-source CAD tools open-source hardware (FPGA, ASIC)